
# #########################################################################
#© Copyright 2021 Xilinx, Inc.

#Licensed under the Apache License, Version 2.0 (the "License");
#you may not use this file except in compliance with the License.
#You may obtain a copy of the License at

#    http://www.apache.org/licenses/LICENSE-2.0

#Unless required by applicable law or agreed to in writing, software
#distributed under the License is distributed on an "AS IS" BASIS,
#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#See the License for the specific language governing permissions and
#limitations under the License.
# ###########################################################################


set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets -of [get_pins design_1_i/static_region/clk_wiz_0/inst/clkout1_buf/O]]

set_property IOSTANDARD DIFF_POD12_DCI [get_ports {C0_DDR4_SLR3_dqs_c[0]}]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports {C0_DDR4_SLR3_dqs_t[0]}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {C0_SYS_CLK_SLR3_clk_n[0]}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {C0_SYS_CLK_SLR3_clk_p[0]}]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {C0_DDR4_SLR3_ck_c[0]}]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {C0_DDR4_SLR3_ck_t[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports C0_DDR4_SLR3_reset_n]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dm_n[0]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dq[0]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dq[1]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dq[2]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dq[3]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dq[4]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dq[5]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dq[6]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR3_dq[7]}]
set_property IOSTANDARD SSTL12_DCI [get_ports C0_DDR4_SLR3_act_n]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[10]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[11]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[12]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[13]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[14]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[15]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[16]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[1]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[2]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[3]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[4]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[5]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[6]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[7]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[8]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_adr[9]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_ba[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_ba[1]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_bg[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_bg[1]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_cke[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_cs_n[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR3_odt[0]}]
set_property SLEW FAST [get_ports C0_DDR4_SLR3_act_n]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[10]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[11]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[12]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[13]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[14]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[15]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[16]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[1]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[2]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[3]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[4]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[5]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[6]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[7]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[8]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_adr[9]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_ba[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_ba[1]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_bg[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_bg[1]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_ck_c[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_ck_t[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_cke[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_cs_n[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dm_n[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dq[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dq[1]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dq[2]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dq[3]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dq[4]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dq[5]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dq[6]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dq[7]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dqs_c[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_dqs_t[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR3_odt[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports C0_DDR4_SLR3_act_n]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[16]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_adr[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_ba[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_ba[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_bg[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_bg[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_ck_c[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_ck_t[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_cke[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_cs_n[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dm_n[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dq[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dq[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dq[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dq[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dq[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dq[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dq[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dq[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dqs_c[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_dqs_t[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR3_odt[0]}]

set_property PACKAGE_PIN L16 [get_ports C0_DDR4_SLR3_act_n]
set_property PACKAGE_PIN B18 [get_ports {C0_DDR4_SLR3_adr[0]}]
set_property PACKAGE_PIN A20 [get_ports {C0_DDR4_SLR3_adr[10]}]
set_property PACKAGE_PIN F19 [get_ports {C0_DDR4_SLR3_adr[11]}]
set_property PACKAGE_PIN F18 [get_ports {C0_DDR4_SLR3_adr[12]}]
set_property PACKAGE_PIN E19 [get_ports {C0_DDR4_SLR3_adr[13]}]
set_property PACKAGE_PIN E18 [get_ports {C0_DDR4_SLR3_adr[14]}]
set_property PACKAGE_PIN F16 [get_ports {C0_DDR4_SLR3_adr[15]}]
set_property PACKAGE_PIN E16 [get_ports {C0_DDR4_SLR3_adr[16]}]
set_property PACKAGE_PIN B17 [get_ports {C0_DDR4_SLR3_adr[1]}]
set_property PACKAGE_PIN D17 [get_ports {C0_DDR4_SLR3_adr[2]}]
set_property PACKAGE_PIN C17 [get_ports {C0_DDR4_SLR3_adr[3]}]
set_property PACKAGE_PIN C19 [get_ports {C0_DDR4_SLR3_adr[4]}]
set_property PACKAGE_PIN C18 [get_ports {C0_DDR4_SLR3_adr[5]}]
set_property PACKAGE_PIN D20 [get_ports {C0_DDR4_SLR3_adr[6]}]
set_property PACKAGE_PIN D19 [get_ports {C0_DDR4_SLR3_adr[7]}]
set_property PACKAGE_PIN C20 [get_ports {C0_DDR4_SLR3_adr[8]}]
set_property PACKAGE_PIN B20 [get_ports {C0_DDR4_SLR3_adr[9]}]
set_property PACKAGE_PIN G20 [get_ports {C0_DDR4_SLR3_ba[0]}]
set_property PACKAGE_PIN F20 [get_ports {C0_DDR4_SLR3_ba[1]}]
set_property PACKAGE_PIN E17 [get_ports {C0_DDR4_SLR3_bg[0]}]
set_property PACKAGE_PIN D16 [get_ports {C0_DDR4_SLR3_bg[1]}]
set_property PACKAGE_PIN A19 [get_ports {C0_DDR4_SLR3_ck_t[0]}]
set_property PACKAGE_PIN A18 [get_ports {C0_DDR4_SLR3_ck_c[0]}]
set_property PACKAGE_PIN K17 [get_ports {C0_DDR4_SLR3_cke[0]}]
set_property PACKAGE_PIN G16 [get_ports {C0_DDR4_SLR3_cs_n[0]}]
set_property PACKAGE_PIN R18 [get_ports {C0_DDR4_SLR3_dm_n[0]}]
set_property PACKAGE_PIN R19 [get_ports {C0_DDR4_SLR3_dq[0]}]
set_property PACKAGE_PIN P19 [get_ports {C0_DDR4_SLR3_dq[1]}]
set_property PACKAGE_PIN M18 [get_ports {C0_DDR4_SLR3_dq[2]}]
set_property PACKAGE_PIN M17 [get_ports {C0_DDR4_SLR3_dq[3]}]
set_property PACKAGE_PIN N19 [get_ports {C0_DDR4_SLR3_dq[4]}]
set_property PACKAGE_PIN N18 [get_ports {C0_DDR4_SLR3_dq[5]}]
set_property PACKAGE_PIN N17 [get_ports {C0_DDR4_SLR3_dq[6]}]
set_property PACKAGE_PIN M16 [get_ports {C0_DDR4_SLR3_dq[7]}]
set_property PACKAGE_PIN P17 [get_ports {C0_DDR4_SLR3_dqs_t[0]}]
set_property PACKAGE_PIN P16 [get_ports {C0_DDR4_SLR3_dqs_c[0]}]
set_property PACKAGE_PIN J16 [get_ports {C0_DDR4_SLR3_odt[0]}]
set_property PACKAGE_PIN K16 [get_ports C0_DDR4_SLR3_reset_n]
set_property PACKAGE_PIN G18 [get_ports {C0_SYS_CLK_SLR3_clk_p[0]}]
set_property PACKAGE_PIN G17 [get_ports {C0_SYS_CLK_SLR3_clk_n[0]}]

set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dm_n[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dq[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dq[1]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dq[2]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dq[3]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dq[4]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dq[5]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dq[6]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dq[7]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dqs_c[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR3_dqs_t[0]}]

